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Digital design : (Record no. 58924)

MARC details
000 -LEADER
fixed length control field 06230cam a2200541 i 4500
001 - CONTROL NUMBER
control field ocn962549477
003 - CONTROL NUMBER IDENTIFIER
control field OCoLC
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20201207174935.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 170202s2018 nju 001 0 eng
010 ## - LIBRARY OF CONGRESS CONTROL NUMBER
LC control number 2017004488
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9780134549897
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 0134549899
035 ## - SYSTEM CONTROL NUMBER
System control number (OCoLC)962549477
040 ## - CATALOGING SOURCE
Original cataloging agency DLC
Language of cataloging eng
Description conventions rda
Transcribing agency DLC
Modifying agency BTCTA
-- BDX
-- OCLCF
-- YDX
-- OCLCO
-- OCLCQ
-- AU@
-- NOW
042 ## - AUTHENTICATION CODE
Authentication code pcc
049 ## - LOCAL HOLDINGS (OCLC)
Holding library UPMM
050 00 - LIBRARY OF CONGRESS CALL NUMBER
Classification number TK7888.3
Item number .M343 2018
082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.395 MAN 2018
Edition number 23
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Mano, M. Morris,
Dates associated with a name 1927-
Relator term author.
245 10 - TITLE STATEMENT
Title Digital design :
Remainder of title with an introduction to the verilog HDL, VHDL, and system Verilog /
Statement of responsibility, etc. M. Morris Mano, Emeritus Professor of Computer Engineering, California State University, Los Angeles, Michael D. Ciletti, Emeritus Professor of Electrical and Computer Engineering, University of Colorado at Colorado Springs.
250 ## - EDITION STATEMENT
Edition statement Sixth edition.
264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE
Place of production, publication, distribution, manufacture NY, NY :
Name of producer, publisher, distributor, manufacturer Pearson,
Date of production, publication, distribution, manufacture, or copyright notice [2018]
300 ## - PHYSICAL DESCRIPTION
Extent 1 online resource
336 ## - CONTENT TYPE
Content type term text
Content type code txt
Source rdacontent
337 ## - MEDIA TYPE
Media type term unmediated
Media type code n
Source rdamedia
338 ## - CARRIER TYPE
Carrier type term volume
Carrier type code nc
Source rdacarrier
500 ## - GENERAL NOTE
General note Includes index.
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note 1. Digital Systems and Binary Numbers -- 1.1. Digital Systems -- 1.2. Binary Numbers -- 1.3. Number-Base Conversions -- 1.4. Octal and Hexadecimal Numbers -- 1.5. Complements of Numbers -- 1.6. Signed Binary Numbers -- 1.7. Binary Codes -- 1.8. Binary Storage and Registers -- 1.9. Binary Logic -- 2. Boolean Algebra and Logic Gates -- 2.1. Introduction -- 2.2. Basic Definitions -- 2.3. Axiomatic Definition of Boolean Algebra -- 2.4. Basic Theorems and Properties of Boolean Algebra -- 2.5. Boolean Functions -- 2.6. Canonical and Standard Forms -- 2.7. Other Logic Operations -- 2.8. Digital Logic Gates -- 2.9. Integrated Circuits -- 3. Gate-Level Minimization -- 3.1. Introduction -- 3.2. The Map Method -- 3.3. Four-Variable K-Map -- 3.4. Product-of-Sums Simplification -- 3.5. Don't-Care Conditions -- 3.6. NAND and NOR Implementation -- 3.7. Other Two-Level Implementations -- 3.8. Exclusive-OR Function -- 3.9. Hardware Description Languages (HDLS) -- 3.10. Truth Tables in HDLS
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Note continued: 4. Combinational Logic -- 4.1. Introduction -- 4.2. Combinational Circuits -- 4.3. Analysis of Combinational Circuits -- 4.4. Design Procedure -- 4.5. Binary Adder -- Subtractor -- 4.6. Decimal Adder -- 4.7. Binary Multiplier -- 4.8. Magnitude Comparator -- 4.9. Decoders -- 4.10. Encoders -- 4.11. Multiplexers -- 4.12. HDL Models of Combinational Circuits -- 4.13. Behavioral Modeling -- 4.14. Writing a Simple Testbench -- 4.15. Logic Simulation -- 5. Synchronous Sequential Logic -- 5.1. Introduction -- 5.2. Sequential Circuits -- 5.3. Storage Elements: Latches -- 5.4. Storage Elements: Flip-Flops -- 5.5. Analysis of Clocked Sequential Circuits -- 5.6. Synthesizable HDL Models of Sequential Circuits -- 5.7. State Reduction and Assignment -- 5.8. Design Procedure -- 6. Registers and Counters -- 6.1. Registers -- 6.2. Shift Registers -- 6.3. Ripple Counters -- 6.4. Synchronous Counters -- 6.5. Other Counters -- 6.6. HDL Models of Registers and Counters -- 7. Memory and Programmable Logic
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Note continued: 7.1. Introduction -- 7.2. Random-Access Memory -- 7.3. Memory Decoding -- 7.4. Error Detection and Correction -- 7.5. Read-Only Memory -- 7.6. Programmable Logic Array -- 7.7. Programmable Array Logic -- 7.8. Sequential Programmable Devices -- 8. Design at the Register Transfer Level -- 8.1. Introduction -- 8.2. Register Transfer Level (RTL) Notation -- 8.3. RTL Descriptions -- 8.4. Algorithmic State Machines (ASMs) -- 8.5. Design Example (ASMD CHART) -- 8.6. HDL Description of Design Example -- 8.7. Sequential Binary Multiplier -- 8.8. Control Logic -- 8.9. HDL Description of Binary Multiplier -- 8.10. Design with Multiplexers -- 8.11. Race-Free Design (Software Race Conditions) -- 8.12. Latch-Free Design (Why Waste Silicon?) -- 8.13. SystemVerilog -- An Introduction -- 9. Laboratory Experiments with Standard ICs and FPGAs -- 9.1. Introduction to Experiments -- 9.2. Experiment 1: Binary and Decimal Numbers -- 9.3. Experiment 2: Digital Logic Gates
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Note continued: 9.4. Experiment 3: Simplification of Boolean Functions -- 9.5. Experiment 4: Combinational Circuits -- 9.6. Experiment 5: Code Converters -- 9.7. Experiment 6: Design with Multiplexers -- 9.8. Experiment 7: Adders and Subtractors -- 9.9. Experiment 8: Flip-Flops -- 9.10. Experiment 9: Sequential Circuits -- 9.11. Experiment 10: Counters -- 9.12. Experiment 11: Shift Registers -- 9.13. Experiment 12: Serial Addition -- 9.14. Experiment 13: Memory Unit -- 9.15. Experiment 14: Lamp Handball -- 9.16. Experiment 15: Clock-Pulse Generator -- 9.17. Experiment 16: Parallel Adder and Accumulator -- 9.18. Experiment 17: Binary Multiplier -- 9.19. HDL Simulation Experiments and Rapid Prototyping with FPGAs -- 10. Standard Graphic Symbols -- 10.1. Rectangular-Shape Symbols -- 10.2. Qualifying Symbols -- 10.3. Dependency Notation -- 10.4. Symbols for Combinational Elements -- 10.5. Symbols for Flip-Flops -- 10.6. Symbols for Registers -- 10.7. Symbols for Counters -- 10.8. Symbol for RAM.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Electronic digital computers
General subdivision Circuits.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Logic circuits.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Logic design.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Digital integrated circuits.
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Digital integrated circuits.
Source of heading or term fast
Authority record control number or standard number (OCoLC)fst00893692
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Electronic digital computers
General subdivision Circuits.
Source of heading or term fast
Authority record control number or standard number (OCoLC)fst00907124
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Logic circuits.
Source of heading or term fast
Authority record control number or standard number (OCoLC)fst01002031
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Logic design.
Source of heading or term fast
Authority record control number or standard number (OCoLC)fst01002045
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Ciletti, Michael D.,
Relator term author.
856 ## - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier <a href="https://firstcityuniversity.sharepoint.com/:b:/s/FirstCityUC-eBooksCollections11/EdCVo38LxcxMlhSek-TWrJIB3kWtGR4fd_8JCgTAv2dwJw?e=5294ew">https://firstcityuniversity.sharepoint.com/:b:/s/FirstCityUC-eBooksCollections11/EdCVo38LxcxMlhSek-TWrJIB3kWtGR4fd_8JCgTAv2dwJw?e=5294ew</a>
Link text Click here to access online
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme Dewey Decimal Classification
Koha item type Electronic Book
949 ## - LOCAL PROCESSING INFORMATION (OCLC)
a TK7888.3 .M343 2018
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949 ## - LOCAL PROCESSING INFORMATION (OCLC)
a TK7888.3 .M343 2018
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949 ## - LOCAL PROCESSING INFORMATION (OCLC)
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980 ## - EQUIVALENCE OR CROSS-REFERENCE-SERIES STATEMENT--PERSONAL NAME/TITLE [LOCAL, CANADA]
Personal name 20190816
Relator term $202.25
Date of a work 136244
Number of part/section of a work 307036
980 ## - EQUIVALENCE OR CROSS-REFERENCE-SERIES STATEMENT--PERSONAL NAME/TITLE [LOCAL, CANADA]
Personal name 20170511
Relator term $174.93
Date of a work 109586
Number of part/section of a work YBP21
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Home library Date acquired Total Checkouts Full call number Barcode Date last seen Price effective from Koha item type
    Dewey Decimal Classification   e-book FIRST CITY UNIVERSITY COLLEGE 07/12/2020   621.395 MAN 2018 e00370 07/12/2020 07/12/2020 Electronic Book