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Development of a verilog to VHDL hardware description language [HDL] translator / Chee Kwun Keong

By:

Chee Kwun Keong [Author]

Material type: Text

Text

TextPublication details: 2001DDC classification:

BEC2001-12

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Holdings ( 1 )

Holdings
Item type	Current library	Home library	Collection	Shelving location	Call number	Status	Date due	Barcode	Item holds
Thesis/Dissertation	FIRST CITY UNIVERSITY COLLEGE	FIRST CITY UNIVERSITY COLLEGE	Thesis/Dissertation	Dissertation	BEC2001-12 (Browse shelf(Opens below))	Not for loan		TD2061

Total holds: 0

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Previous	BEC2001-09 Construction and development of herbal cybermall /	BEC2001-10 Construction and development of herbal cybermall /	BEC2001-11 Construction and development of herbal cybermall /	BEC2001-12 Development of a verilog to VHDL hardware description language [HDL] translator /	BEC2001-14 Implementation of RSA algorithm using mentor graphics FPGA design tools /	BEC2001-15 Implementation of RSA algorithm using mentor graphics FPGA design tools /	BEC2001-16 The implementation of RSA encryption and decryption algorithm using mentor graphics EDA tools /	Next

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