Arithmetic built-in-self-test for embedded systems / Janusz Rajski, Jerzy Tyszer.
Material type:![Text](/opac-tmpl/lib/famfamfam/BK.png)
- 0137564384
Item type | Current library | Home library | Collection | Shelving location | Call number | Status | Date due | Barcode | Item holds |
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FIRST CITY UNIVERSITY COLLEGE | FIRST CITY UNIVERSITY COLLEGE | Open Collection | FCUC Library | 621.395 RAJ (Browse shelf(Opens below)) | Available | 00005298 |
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621.395 RAB Digital Integrated Circuits: A Design Perspective. | 621.395 RAB Digital integrated circuits : | 621.395 RAB 1996 Digital Integrated Circuits: A Design Perspective | 621.395 RAJ Arithmetic built-in-self-test for embedded systems / | 621.395 ROT Fundamentals of logic design / | 621.395 ROT Fundamentals of logic design / | 621.395 ROT Fundamentals of logic design / |
Includes bibliographical references and index.
Arithmetic Built-In Self-Test for Embedded Systems offers a thorough treatment of the important issues in software-based built-in self-test for systems with embedded processors. Fundamental concepts are illustrated with practical scenarios for test generation, test application, and test response compaction. Arithmetic Built-In Self-Test for Embedded Systems uses an approach to cutting-edge technology that will be of interest to hardware and embedded system designers, test and design engineers, and researchers working on IC/core testing. It is also appropriate for graduate-level design courses. An introductory chapter provides a comprehensive tutorial covering the most relevant DFT and BIST techniques.